A host and a device typically transmit and receive data to and from each other. For example in a personal computer environment, a disk drive controller (host) is often connected to a disk drive (device). Referring now to FIG. 1A, a host 10 includes a receiver 12 and a transmitter 14. A device 16 includes a receiver 18 and a transmitter 20. The transmitter 14 of the host 10 transmits host data 22 to the receiver 18 of the device 16. The transmitter 20 of the device 16 transmits device data 24 to the receiver 12 of the host 10. In the personal computer environment the host 10 can be a disk controller 10-1 and the device 16 can be a disk drive 16-1 as shown in FIG. 1B. Still other hosts and devices can be employed.
The host and the device are connected using a Serial Advanced Technology Attachment (SATA) standard, which is generally identified at 26. The SATA standard is a simplified packet switching network between a host and a device. SATA typically employs balanced voltage (differential) amplifiers and two pairs of wires that connect transmitters and receivers of the host 10 and the device 16 in a manner similar to 100BASE-TX Ethernet. The SATA standard is disclosed in “Serial ATA: High Speed Serialized AT Attachment”, Serial ATA Organization, Revision 1.0, 29, Aug. 2001, and its Supplements and Errata, which are hereby incorporated by reference.
Referring now to FIG. 1C, a typical physical layer (PHY) 28 of the host 10 and/or the device 16 is shown generally at 29. An analog front end 30 provides an interface to the data transmission lines. The analog front end 30 includes differential drivers and receivers and/or out-of-band signaling circuits. A PHY control circuit 31 controls the functionality of the PHY 28. Fixed pattern source and detect circuits 32 and 33, respectively, are optional circuits that provide ALIGN primitives. The fixed pattern detect circuit 33 generates a COMMA signal when a K28.5 character is detected in the received data.
DataIn[0:n] and an output of the fixed pattern source 32 are input to a multiplexer 34. The PHY control circuit 31 controls the multiplexer 34. DataIn[0:n] includes data sent from the link layer to the PHY 28 for serialization and transmission. A data extraction circuit 35 separates the clock (RecClk clock signal) and data received by the receivers in the analog front end 30. The TxClk output from the control circuit 31 regulates the frequency of the serial stream. DataOut[0:n], which is passed to the link layer, includes data that is received and deserialized by the PHY 28. The SYSCLK signal is a reference clock signal that is used to establish the transmitter interface speed. Other control inputs and outputs generally identified by MISC in FIG. 1C are specified in the SATA standard.
Referring now to FIG. 2, the transmitter 14 of the host 10 or the transmitter 20 of the device 16 is shown. Differential data (D(0)+ and D(0)−) to be transmitted is received by differential inputs of a differential driving device 40. The differential driving device 40 creates a differential voltage (V+ and V−) by driving differential outputs (i0+ and i0−) through loads 42 and 44. A communications channel 46 transmits the differential voltage to the receiver 18 of the device 16 or to the receiver 12 of the host 10. The transmission characteristics of the communications channel 46 may attenuate or otherwise alter the signal that is received by the receiver at the opposite end of the communications channel 46, which may increase bit error rates.
Referring now to FIG. 3, the differential output voltage in an ideal communications channel 46 is shown. In FIG. 4, the differential output voltage of a band-limiting communications channel is shown, which is a typical characteristic of the communications channel 46. The transition from 0 to 1 to 0 creates an “eye”-shaped waveform that is generally identified at 48 in FIGS. 4 and 5. As the band-limiting transmission characteristic increases, the “eye” closes as shown by arrows 49, which makes the 0-1-0 transition more difficult to detect.